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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MCF52235DS Rev. 7, 8/2008
MCF52235
MCF52235 ColdFire Microcontroller Data Sheet
Supports MCF52230, MCF52231, MCF52232, MCF52233, MCF52234, MCF52235, and MCF52236
The MCF52235 is a member of the ColdFire(R) family of reduced instruction set computing (RISC) microcontrollers. This document provides an overview of the MCF52235 microcontroller family, focusing on its highly integrated and diverse feature set. This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 60 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM). On-chip modules include: * V2 ColdFire core providing 56 Dhrystone 2.1 MIPS @ 60 MHz executing out of on-chip Flash memory using enhanced multiply accumulate (EMAC) and hardware divider * Enhanced Multiply Accumulate Unit (EMAC) and hardware divide module * Cryptographic Acceleration Unit (CAU) coprocessor * Fast Ethernet Controller (FEC) * On-chip Ethernet Transceiver (EPHY) * FlexCAN controller area network (CAN) module * Three universal asynchronous/synchronous receiver/transmitters (UARTs) * Inter-integrated circuit (I2CTM) bus controller * Queued serial peripheral interface (QSPI) module * Eight-channel 10- or 12-bit fast analog-to-digital converter (ADC) * Four channel direct memory access (DMA) controller * Four 32-bit input capture/output compare timers with DMA support (DTIM) * Four-channel general-purpose timer (GPT) capable of input capture/output compare, pulse width modulation (PWM) and pulse accumulation * Eight/Four-channel 8/16-bit pulse width modulation timers (two adjacent 8-bit PWMs can be concatenated to form a single 16-bit timer) * * * *
LQFP-80 14mm x 14mm LQFP-112 20mm_x_20mm
MAPBGA-121 12mm_x_12mm
Two 16-bit periodic interrupt timers (PITs) Real-time clock (RTC) module Programmable software watchdog timer Two interrupt controllers providing every peripheral with a unique selectable-priority interrupt vector plus seven external interrupts with fixed levels/priorities * Clock module with support for crystal or external oscillator and integrated phase-locked loop (PLL) * Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 MCF52235 Family Configurations . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .22 1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .23 1.8 Fast Ethernet Controller EPHY Signals . . . . . . . . . . . .23 1.9 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .25 1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .25 1.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .25 1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .27 1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .27 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .32 2.4 Phase Lock Loop Electrical Specifications . . . . . . . . . .33 2.5 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .35 2.6 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.7 I2C Input/Output Timing Specifications . . . . . . . . . . . . .36 2.8 EPHY Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.9 Analog-to-Digital Converter (ADC) Parameters . . . . . .40 2.10 DMA Timers Timing Specifications . . . . . . . . . . . . . . . .42 2.11 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .42 2.12 QSPI Electrical Specifications. . . . . . . . . . . . . . . . . . . .43 2.13 JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . .44 2.14 Debug AC Timing Specifications. . . . . . . . . . . . . . . . . .46 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .47 3.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .47 3.2 112-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . .48 3.3 121 MAPBGA Package. . . . . . . . . . . . . . . . . . . . . . . . .51 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Figure 14.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . Figure 15.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . Figure 16.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . Figure 17.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . . Figure 19.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . . 44 45 45 45 46 46
List of Tables
Table 1. MCF52235 Family Configurations . . . . . . . . . . . . . . . . . 3 Table 2. Orderable Part Number Summary. . . . . . . . . . . . . . . . 13 Table 3. Pin Functions by Primary and Alternate Purpose . . . . 17 Table 4. Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6. Mode Selection Signals . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7. External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. Queued Serial Peripheral Interface (QSPI) Signals. . . 23 Table 9. Fast Ethernet Controller (FEC) Signals . . . . . . . . . . . . 23 Table 10.I2C I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11.UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12.DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13.ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14.GPT Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15.PWM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 16.Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17.EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . 27 Table 18.Power and Ground Pins. . . . . . . . . . . . . . . . . . . . . . . . 27 Table 19.Absolute Maximum Ratings, . . . . . . . . . . . . . . . . . . . 29 Table 20.Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 30 Table 21.ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 31 Table 22.DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 32 Table 23.Active Current Consumption Specifications. . . . . . . . . 33 Table 24.Current Consumption Specifications in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 25.PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . 33 Table 26.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 27.Reset and Configuration Override Timing . . . . . . . . . . 35 Table 28.I2C Input Timing Specifications between I2C_SCL and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 29. I2C Output Timing Specifications between I2C_SCL and I2C_SDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 30.EPHY Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 38 Table 31.10BASE-T SQE (Heartbeat) Timing Parameters . . . . 38 Table 32.10BASE-T Jab and Unjab Timing Parameters . . . . . . 39 Table 33.10BASE-T Transceiver Characteristics . . . . . . . . . . . . 40 Table 34.100BASE-TX Transceiver Characteristics . . . . . . . . . . 40 Table 35.ADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 36.Timer Module AC Timing Specifications . . . . . . . . . . . 42 Table 37.EzPort Electrical Specifications . . . . . . . . . . . . . . . . . . 42 Table 38.QSPI Modules AC Timing Specifications. . . . . . . . . . . 43 Table 39.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 44 Table 40.Debug AC Timing Specification . . . . . . . . . . . . . . . . . . 46 Table 41.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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4
List of Figures
Figure 1. MCF52235 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. 80-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . . 14 Figure 3. 112-pin LQFP Pin Assignments . . . . . . . . . . . . . . . . . 15 Figure 4. 121 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . 16 Figure 5. Suggested Connection Scheme for Power and Ground 28 Figure 6. GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7. RSTI and Configuration Override Timing . . . . . . . . . . 36 Figure 8. I2C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . 37 Figure 9. EPHY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10.10BASE-T SQE (Heartbeat) Timing . . . . . . . . . . . . . 39 Figure 11.10BASE-T Jab and Unjab Timing . . . . . . . . . . . . . . . 39 Figure 12.Equivalent Circuit for A/D Loading. . . . . . . . . . . . . . . 42 Figure 13.QSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 2 Freescale Semiconductor
MCF52235 Family Configurations
1
MCF52235 Family Configurations
Table 1. MCF52235 Family Configurations
Module 52230 * 60 56 128/32 Kbytes * * -- -- * * * 2 * 4 * 3 * * * * * * 52231 * 60 56 128/32 Kbytes * * -- * * * * 2 * 4 * 3 * * * * * * 52232 * 50 46 128/32 Kbytes * * -- -- * * * 2 * 4 * 3 * * * * * * 52233 * 60 56 256/32 Kbytes * * -- -- * * * 2 * 4 * 3 * * * * * * 52234 * 60 56 256/32 Kbytes * * -- * * * * 2 * 4 * 3 * * * * * * 52235 * 60 56 256/32 Kbytes * * * * * * * 2 * 4 * 3 * * * * * * 52236 * 50 46 256/32 Kbytes * * -- -- * * * 2 * 4 * 3 * * * * * *
Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) System Clock (MHz) Performance (Dhrystone 2.1 MIPS) Flash / Static RAM (SRAM) Interrupt Controllers (INTC0/INTC1) Fast Analog-to-Digital Converter (ADC) Random Number Generator and Crypto Acceleration Unit (CAU) FlexCAN 2.0B Module Fast Ethernet Controller (FEC) with on-chip interface (EPHY) Four-channel Direct-Memory Access (DMA) Software Watchdog Timer (WDT) Programmable Interrupt Timer Four-Channel General Purpose Timer 32-bit DMA Timers QSPI UART(s) I2C Eight/Four-channel 8/16-bit PWM Timer General Purpose I/O Module (GPIO) Chip Configuration and Reset Controller Module Background Debug Mode (BDM) JTAG - IEEE 1149.1 Test Access Port1 Package
80 LQFP 80 LQFP 80 LQFP 80 LQFP 112 LQFP 112 LQFP 80 LQFP 112 LQFP 112 LQFP 112 LQFP 121 121 MAPBGA MAPBGA
1
The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the 80-pin package.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 3
MCF52235 Family Configurations
1.1
Block Diagram
The MCF52235 (or its variants) comes in 80- and 112-pin low-profile quad flat pack packages (LQFP) and a 121 MAPBGA, and operates in single-chip mode only. Figure 1 shows a top-level block diagram of the MCF52235.
EPHY_TX EzPD EPHY_RX EzPQ EzPort EzPCK EzPCS Interrupt Controller 1 Interrupt Controller 2 PADI - Pin Muxing GPTn QSPI_DIN, QSPI_DOUT QSPI_CLK, QSPI_CSn SDA SCL UTXDn URXDn URTSn UCTSn DTINn/DTOUTn CANRX CANTX PWMn
EPHY
Arbiter
Fast Ethernet
Controller
(FEC) 4 CH DMA To/From PADI
UART 0
UART 1
UART 2
I2C
QSPI
DTIM 0
DTIM 1
DTIM 2
DTIM 3
RTC
JTAG_EN
MUX
V2 ColdFire CPU
JTAG TAP IFP OEP CAU EMAC PMM
AN[7:0]
ADC
32 Kbytes SRAM (4Kx16)x4
256 Kbytes Flash (32Kx16)x4
PORTS (GPIO)
CIM
RSTIN RSTOUT
VRH
VRL
Edge Port 1 Edge Port 2
PLL CLKGEN
FlexCAN
PIT1
PWM
EXTAL XTAL CLKOUT
RNGA
PIT0
GPT
To/From Interrupt Controller
Figure 1. MCF52235 Block Diagram
1.2
Features
This document contains information on a new product under development. Freescale reserves the right to change or discontinue this product without notice. Specifications and information herein are subject to change without notice.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 4 Freescale Semiconductor
MCF52235 Family Configurations
1.2.1
*
Feature Overview
Version 2 ColdFire variable-length RISC processor core -- Static operation -- 32-bit address and data paths on-chip -- Up to 60 MHz processor core frequency -- Sixteen general-purpose, 32-bit data and address registers -- Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+) -- Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support 16 x 16 32 or 32 x 32 32 operations -- Cryptography Acceleration Unit (CAU) - Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions - FIPS-140 compliant random number generator -- Support for DES, 3DES, AES, MD5, and SHA-1 algorithms -- Illegal instruction decode that allows for 68K emulation support System debug support -- Real time trace for determining dynamic execution path -- Background debug mode (BDM) for in-circuit debugging (DEBUG_B+) -- Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into a 1- or 2-level trigger On-chip memories -- Up to 32 Kbytes of dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support -- Up to 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses Power management -- Fully static operation with processor sleep and whole chip stop modes -- Rapid response to interrupts from the low-power sleep mode (wake-up feature) -- Clock enable/disable for each peripheral when not used Fast Ethernet Controller (FEC) -- 10/100 BaseT/TX capability, half duplex or full duplex -- On-chip transmit and receive FIFOs -- Built-in dedicated DMA controller -- Memory-based flexible descriptor rings
The MCF52235 family includes the following features:
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On-chip Ethernet Transceiver (EPHY) -- Digital adaptive equalization -- Supports auto-negotiation -- Baseline wander correction -- Full-/Half-duplex support in all modes -- Loopback modes -- Supports MDIO preamble suppression -- Jumbo packet
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FlexCAN 2.0B module
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
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MCF52235 Family Configurations
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-- Based on and includes all existing features of the Freescale TouCAN module -- Full implementation of the CAN protocol specification version 2.0B - Standard Data and Remote Frames (up to 109 bits long) - Extended Data and Remote Frames (up to 127 bits long) - 0-8 bytes data length - Programmable bit rate up to 1 Mbit/sec -- Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0-8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages -- Unused Message Buffer space can be used as general purpose RAM space -- Listen only mode capability -- Content-related addressing -- No read/write semaphores required -- Three programmable mask registers: global for MBs 0-13, special for MB14, and special for MB15 -- Programmable transmit-first scheme: lowest ID or lowest buffer number -- Time stamp based on 16-bit free-running timer -- Global network time, synchronized by a specific message -- Maskable interrupts Three universal asynchronous/synchronous receiver transmitters (UARTs) -- 16-bit divider for clock generation -- Interrupt control logic with maskable interrupts -- DMA support -- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity -- Up to 2 stop bits in 1/16 increments -- Error-detection capabilities -- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs -- Transmit and receive FIFO buffers I2C module -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads -- Fully compatible with industry-standard I2C bus -- Master and slave modes support multiple masters -- Automatic interrupt generation with programmable level Queued serial peripheral interface (QSPI) -- Full-duplex, three-wire synchronous transfers -- Up to four chip selects available -- Master mode operation only -- Programmable bit rates up to half the CPU clock frequency -- Up to 16 pre-programmed transfers Fast analog-to-digital converter (ADC) -- Eight analog input channels -- 12-bit resolution -- Minimum 1.125 s conversion time -- Simultaneous sampling of two channels for motor control applications -- Single-scan or continuous operation -- Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit -- Unused analog channels can be used as digital I/O
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 6 Freescale Semiconductor
MCF52235 Family Configurations
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Four 32-bit DMA timers -- 17-ns resolution at 60 MHz -- Programmable sources for clock input, including an external clock option -- Programmable prescaler -- Input capture capability with programmable trigger edge on input pin -- Output compare with programmable mode for the output pin -- Free run and restart modes -- Maskable interrupts on input capture or output compare -- DMA trigger capability on input capture or output compare Four-channel general purpose timers -- 16-bit architecture -- Programmable prescaler -- Output pulse widths variable from microseconds to seconds -- Single 16-bit input pulse accumulator -- Toggle-on-overflow feature for pulse-width modulator (PWM) generation -- One dual-mode pulse accumulation channel Pulse-width modulation timer -- Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution -- Programmable period and duty cycle -- Programmable enable/disable for each channel -- Software selectable polarity for each channel -- Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled. -- Programmable center or left aligned outputs on individual channels -- Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies -- Emergency shutdown Real-Time Clock (RTC) -- Maintains system time-of-day clock -- Provides stopwatch and alarm interrupt functions
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Two periodic interrupt timers (PITs) -- 16-bit counter -- Selectable as free running or count down Software watchdog timer -- 32-bit counter -- Low power mode support Clock Generation Features -- 25 MHz crystal input -- On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency -- Provides clock for integrated EPHY
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Dual Interrupt Controllers (INTC0/INTC1) -- Support for multiple interrupt sources organized as follows: - Fully-programmable interrupt sources for each peripheral - 7 fixed-level interrupt sources - Seven external interrupt signals
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
7
MCF52235 Family Configurations
-- Unique vector number for each interrupt source -- Ability to mask any individual interrupt source or all interrupt sources (global mask-all) -- Support for hardware and software interrupt acknowledge (IACK) cycles * -- Combinatorial path to provide wake-up from low power modes DMA controller -- Four fully programmable channels -- Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 x 32-bit) burst transfers -- Source/destination address pointers that can increment or remain constant -- 24-bit byte transfer counter per channel -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle steal support -- Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4) Reset -- Separate reset in and reset out signals -- Seven sources of reset: - Power-on reset (POR) - External - Software - Watchdog - Loss of clock - Loss of lock - Low-voltage detection (LVD) -- Status flag indication of source of last reset Chip integration module (CIM) -- System configuration during reset -- Selects one of three clock modes -- Configures output pad drive strength -- Unique part identification number and part revision number General purpose I/O interface -- Up to 56 bits of general purpose I/O -- Bit manipulation supported via set/clear functions -- Programmable drive strengths -- Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing
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1.2.2
V2 Core Overview
The version 2 ColdFire processor core is comprised of two separate pipelines decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF52235 core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing capabilities. The EMAC implements a three-stage arithmetic
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 8 Freescale Semiconductor
MCF52235 Family Configurations
pipeline, optimized for 16x16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
1.2.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, access debug information and real-time tracing capability is provided on 112-and 121-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor's supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception. The MCF52235 implements revision B+ of the ColdFire Debug Architecture. The MCF52235's interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging. To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU's clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical AND of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111). The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.4
JTAG
The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device's pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF52235 implementation can do the following: * * * * * Perform boundary-scan operations to test circuit board electrical continuity Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit Disable the output drive to pins during circuit-board testing Drive output pins to stable levels
1.2.5
1.2.5.1
On-Chip Memories
SRAM
The dual-ported SRAM module provides a general-purpose 16- or 32-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 16- or 32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 9
MCF52235 Family Configurations
module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.
1.2.5.2
Flash
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor's high-speed local bus. The CFM is constructed with four banks of 32 Kx16-bit flash arrays to generate 256 Kbytes of 32-bit flash memory. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle flash arrays. A backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial flash programming interface that allows the flash to be read, erased and programmed by an external controller in a format compatible with most SPI bus flash memory chips. This allows easy device programming via Automated Test Equipment or bulk programming tools.
1.2.6
Cryptography Acceleration Unit
The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.
1.2.7
Power Management
The MCF52235 incorporates several low-power modes of operation which are entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the LVD trip point.
1.2.8
FlexCAN
The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers.
1.2.9
UARTs
The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 10 Freescale Semiconductor
MCF52235 Family Configurations
1.2.10
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices on a circuit board.
1.2.11
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.12
Fast ADC
The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding separate 10- or 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing. The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed scan sequence repeatedly until manually stopped. The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled. During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously. Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.13
DMA Timers (DTIM0-DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.
1.2.14
General Purpose Timer (GPT)
The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 11
MCF52235 Family Configurations
1.2.15
Periodic Interrupt Timers (PIT0 and PIT1)
The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can count down from the value written in its PIT modulus register or can be a free-running down-counter.
1.2.16
Pulse Width Modulation (PWM) Timers
The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0 to 100%. The PWM outputs have programmable polarity and can be programmed as left-aligned outputs or center-aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.17
Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.2.18
Phase Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.
1.2.19
Interrupt Controller (INTC0/INTC1)
There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level [1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.
1.2.20
DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.
1.2.21
Reset
The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset: * * * * * * External reset input Power-on reset (POR) Watchdog timer Phase locked-loop (PLL) loss of lock PLL loss of clock Software
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 12 Freescale Semiconductor
MCF52235 Family Configurations
*
Low-voltage detector (LVD)
Control of the LVD and its associated reset and interrupt are managed by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.
1.2.22
GPIO
Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary functions and are grouped into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that configure, monitor, and control the port pins.
1.2.23
Part Numbers and Packaging
Table 2. Orderable Part Number Summary
Speed Flash/SRAM (MHz) (Kbytes) 60 60 60 60 50 50 60 60 60 60 60 60 50 50 128 / 32 128 / 32 128 / 32 128 / 32 128 / 32 128 / 32 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 256 / 32 Temp range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70
Freescale Part Number MCF52230CAF60 MCF52230CAL60 MCF52231CAF60 MCF52231CAL60 MCF52232CAF50 MCF52232AF50 MCF52233CAF60 MCF52233CAL60 MCF52234CAL60 MCF52234CVM60 MCF52235CAL60
Description MCF52230 Microcontroller MCF52230 Microcontroller MCF52231 Microcontroller, FlexCAN MCF52231 Microcontroller, FlexCAN MCF52232 Microcontroller MCF52232 Microcontroller MCF52233 Microcontroller MCF52233 Microcontroller MCF52234 Microcontroller, FlexCAN MCF52234 Microcontroller, FlexCAN MCF52235 Microcontroller, FlexCAN, CAU, RNGA
Package 80 LQFP 112 LQFP 80 LQFP 112 LQFP 80 LQFP 80 LQFP 80 LQFP 112 LQFP 112 LQFP 121 MAPBGA 112 LQFP 121 MAPBGA 80 LQFP 80 LQFP
MCF52235CVM60 MCF52235 Microcontroller, FlexCAN, CAU, RNGA MCF52236CAF50 MCF52236AF50
Package Pinouts
MCF52236 Microcontroller MCF52236 Microcontroller
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 13
MCF52235 Family Configurations
Figure 2 shows the pinout configuration for the 80-pin LQFP.
SCL GPT0 GPT1 GPT2 GPT3 VDD1 VSS1 VSSA VRL VRH VDDA AN0 AN1 AN2 AN3 AN7 AN6 AN5 AN4 SDA TCLK/PSTCLK TMS/BKPT RCON/EZPCS TDI/DSI TDO/DSO TRST/DSCLK ALLPST DTIN0/DTOUT0 DTIN1/DTOUT1 VDDX1 VSSX1 JTAG_EN DTIN2/DTOUT2 DTIN3/DTOUT3 URTS1 UCTS1 URTS0 UCTS0 SYNCB SYNCA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80-pin LQFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
ACTLED LNKLED VDDR SPDLED PHY_VSSRX PHY_VDDRX PHY_RXN PHY_RXP PHY_VSSTX PHY_TXN PHY_TXP PHY_VDDTX PHY_VDDA PHY_VSSA PHY_RBIAS VDD2 VSS2 DUPLED COLLED IRQ11
Figure 3 shows the pinout configuration for the 112-pin LQFP.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 14 Freescale Semiconductor
URXD0 UTXD0 URXD1 UTXD1 QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS0 IRQ4 VSSX2 VDDX2 RSTI VDDPLL RSTO VSSPLL EXTAL XTAL TEST IRQ1 IRQ7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2. 80-pin LQFP Pin Assignments
MCF52235 Family Configurations
111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
112
SDA SCL GPT0 GPT1 GPT2 GPT3 IRQ15 IRQ14 PWM7 PWM5 VDD1 VSS1 PWM3 PWM1 IRQ13 IRQ12 VSSA VRL VRH VDDA AN0 AN1 AN2 AN3 AN7 AN6 AN5 AN4
Figure 4 shows the pinout configuration for the 121 MAPBGA.
Freescale Semiconductor
IRQ10 URXD0 UTXD0 URXD1 UTXD1 QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS0 QSPI_CS1 QSPI_CS2 QSPI_CS3 IRQ4 VSSX2 VDDX2 RSTI VDDPLL RSTO VSSPLL EXTAL XTAL TEST TXLED RXLED IRQ3 IRQ2 IRQ1 IRQ7 Figure 3. 112-pin LQFP Pin Assignments
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 15
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
TCLK/PSTCLK TMS/BKPT RCON/EZPCS TDI/DSI TDO/DSO TRST/DSCLK ALLPST DTIN0/DTOUT0 DTIN1/DTOUT1 IRQ8 IRQ9 DDATA3 DDATA2 VDDX1 VSSX1 DDATA1 DDATA0 JTAG_EN IRQ6 IRQ5 DTIN2/DTOUT2 DTIN3/DTOUT3 URTS1 UCTS1 URTS0 UCTS0 SYNCB SYNCA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112-pin LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
ACTLED LNKLED VDDR SPDLED PST3 PST2 PST1 PST0 PHY_VSSRX PHY_VDDRX PHY_RXN PHY_RXP PHY_VSSTX PHY_TXN PHY_TXP PHY_VDDTX PHY_VDDA PHY_VSSA PHY_RBIAS VDD2 VSS2 UTXD2 URXD2 UCTS2 URTS2 DUPLED COLLED IRQ11
16 1 A B C D E MCF52235 ColdFire Microcontroller, Rev. 7 Freescale Semiconductor F G H J K L
TCLK TMS TRST DTIN1 DDATA3 DDATA0 DTIN2 DTIN3 SYNCB SYNCA IRQ10
2
SDA RCON TDO DTIN0 IRQ9 DDATA1 IRQ5 URTS0 UCTS0 URXD0 UTXD0
3
SCL GPT0 TDI ALLPST IRQ8 DDATA2 IRQ6 URTS1 UCTS1 URXD1 UTXD1
4
IRQ15 GPT3 GPT2 GPT1 VSS VSS JTAG_EN QSPI_DIN QSPI_DOUT QSPI_CLK QSPI_CS0
5
IRQ14 PWM5 PWM7 VDDX VSS VSS VDDX QSPI_CS1 QSPI_CS2 QSPI_CS3 IRQ4
6
IRQ13 PWM1 PWM3 VDDX VDDX VSS VDDX VDDX RSTI VDDPLL RSTO
7
VSSA VRL IRQ12 VDD VSS VSS VDDX TEST XTAL VSSPLL EXTAL
8
VDDA VRH AN0 VDDR VDD VSS PHY_VSSA TXLED IRQ1 IRQ2 IRQ3
9
AN1 AN2 AN3 PST2 PST0
10
AN7 AN6 LNKLED PST3 PST1
11
AN5 AN4 ACTLED SPDLED PHY_RXN PHY_RXP PHY_TXP PHY_TXN PHY_RBIAS URXD2 UTXD2
PHY_VSSRX PHY_VDDRX PHY_VSSTX PHY_VDDTX RXLED COLLED IRQ11 IRQ7 PHY_VDDA DUPLED URTS2 UCTS2
Figure 4. 121 MAPBGA Pin Assignments
Freescale Semiconductor MCF52235 ColdFire Microcontroller, Rev. 7 17
Table 3. Pin Functions by Primary and Alternate Purpose
Pin Group ADC3 Primary Function AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 SYNCA SYNCB VDDA VSSA VRH VRL Clock Generation EXTAL XTAL VDDPLL5 VSSPLL Debug Data ALLPST DDATA[3:0] PST[3:0] SecondaryF unction -- -- -- -- -- -- -- -- CANTX
4 4
Tertiary Function -- -- -- -- -- -- -- -- FEC_MDIO FEC_MDC -- -- -- -- -- -- -- -- -- -- --
Drive Quaternary Strength/ Function Control1 PAN[7] PAN[6] PAN[5] PAN[4] PAN[3] PAN[2] PAN[1] PAN[0] PAS[3] PAS[2] -- -- -- -- -- -- -- -- -- PDD[7:4] PDD[3:0] Low Low Low Low Low Low Low Low PDSR[39] PDSR[39] N/A N/A N/A N/A N/A N/A N/A N/A High High High
Wired OR Control -- -- -- -- -- -- -- -- -- -- N/A N/A N/A N/A N/A N/A N/A N/A -- -- --
Pull-up/ Pull-down2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Pin on 121 MAPBGA A10 B10 A11 B11 C9 B9 A9 C8 K1 J1 A8 A7 B8 B7 L7 J7 K6 K7 D3 E1, F3,F2, F1 D10, D9, E10, E9
Pin on 112 LQFP 88 87 86 85 89 90 91 92 28 27 93 96 94 95 48 49 45 47 7 12,13,16,17 80,79,78,77
Pin on 80 LQFP 64 63 62 61 65 66 67 68 20 19 69 72 70 71 36 37 33 35 7 -- --
CANRX -- -- -- -- -- -- -- -- -- -- --
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group Ethernet LEDs Primary Function ACTLED COLLED DUPLED LNKLED SPDLED RXLED MCF52235 ColdFire Microcontroller, Rev. 7 TXLED VDDR Ethernet PHY PHY_RBIAS PHY_RXN PHY_RXP PHY_TXN PHY_TXP PHY_VDDA5 PHY_VDDRX5 PHY_VDDTX PHY_VSSA PHY_VSSRX PHY_VSSTX I
2C 5
18 SCL SDA Interrupts3 IRQ15 IRQ14 IRQ13 IRQ12 Freescale Semiconductor
SecondaryF unction -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CANTX4 CANRX4 -- -- -- --
Tertiary Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTXD2 URXD2 -- -- -- --
Drive Quaternary Strength/ Function Control1 PLD[0] PLD[4] PLD[3] PLD[1] PLD[2] PLD[5] PLD[6] -- -- -- -- -- -- -- -- -- -- -- -- PAS[0] PAS[1] PGP[7] PGP[6] PGP[5] PGP[4] PDSR[0] PDSR[0] PSDR[47] PSDR[46] PSDR[45] PSDR[44] PDSR[32] PDSR[36] PDSR[35] PDSR[33] PDSR[34] PDSR[37] PDSR[38] -- -- -- -- -- --
Wired OR Control PWOR[8] PWOR[12] PWOR[11] PWOR[9] PWOR[10] PWOR[13] PWOR[14] -- -- -- -- -- -- N/A N/A N/A N/A N/A N/A -- -- -- -- -- --
Pull-up/ Pull-down2 -- -- -- -- -- -- -- --
Pin on 121 MAPBGA C11 J9 J10 C10 D11 H9 H8 D8 J11 E11 F11 H11 G11 H10 F10 G10 G8 F9 G9
Pin on 112 LQFP 84 58 59 83 81 52 51 82 66 74 73 71 70 68 75 69 67 76 72 111 112 106 105 98 97
Pin on 80 LQFP 60 42 43 59 57 -- -- 58 46 54 53 51 50 48 55 49 47 56 52 79 80 -- -- -- --
Pull-Up6 Pull-Up6 Pull-Up6 Pull-Up
6
A3 A2 A4 A5 A6 C7
Pull-Up6 Pull-Up
6
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group Continued Interrupts3 Primary Function IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 MCF52235 ColdFire Microcontroller, Rev. 7 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 JTAG/BDM JTAG_EN TCLK/ PSTCLK TDI/DSI TDO/DSO TMS/BKPT TRST/DSCLK Mode Selection PWM RCON/EZPCS PWM7 PWM5 PWM3 PWM1 SecondaryF unction -- -- -- -- -- -- -- -- -- -- SYNCA -- CLKOUT -- -- -- -- -- -- -- -- -- Tertiary Function -- -- -- -- -- FEC_RXER FEC_RXD[1] -- FEC_RXD[2] FEC_RXD[3] PWM1 -- -- -- -- -- -- -- -- -- -- -- Drive Quaternary Strength/ Function Control1 PGP[3] PGP[2] PGP[1] PGP[0] PNQ[7] PNQ[6] PNQ[5] PNQ[4] PNQ[3] PNQ[2] PNQ[1] -- -- -- -- -- -- -- PTD[3] PTD[2] PTD[1] PTD[0] PSDR[43] PSDR[42] PSDR[41] PSDR[40] Low Low Low Low Low Low High N/A High N/A High N/A N/A N/A PDSR[31] PDSR[30] PDSR[29] PDSR[28] Wired OR Control -- -- -- -- -- -- -- -- -- -- -- N/A -- N/A N/A N/A N/A N/A -- -- -- -- Pull-up/ Pull-down2 Pull-Up6 Pull-Up6 Pull-Up6 Pull-Up Pull-Up
6
Freescale Semiconductor 19
Pin on 121 MAPBGA K9 L1 E2 E3 L9 G3 G2 L5 L8 K8 J8 G4 A1 C3 C2 B1 C1 B2 C5 B5 C6 B6
Pin on 112 LQFP 57 29 11 10 56 19 20 41 53 54 55 18 1 4 5 2 6 3 104 103 100 99
Pin on 80 LQFP 41 -- -- -- 40 -- -- 29 -- -- 39 12 1 4 5 2 6 3 -- -- -- --
Pull-Up6 Pull-Up
6 6
Pull-Up
Pull-Up6 Pull-Up6 Pull-Up
6
Pull-Down Pull-Up7 Pull-Up7 -- Pull-Up7 Pull-Up Pull-Up -- -- -- --
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group QSPI3 Primary Function QSPI_DIN/ EZPD QSPI_DOUT/E ZPQ QSPI_CLK/ EZPCK QSPI_CS3 MCF52235 ColdFire Microcontroller, Rev. 7 QSPI_CS2 QSPI_CS1 QSPI_CS0 Reset
9
20 RSTI RSTO Test Timers, 16-bit3 TEST GPT3 GPT2 GPT1 GPT0 Timers, 32-bit DTIN3 DTIN2 DTIN1 DTIN0 UART 0
3
SecondaryF unction CANRX4 CANTX4 SCL SYNCA -- -- SDA -- -- -- FEC_TXD[3] FEC_TXD[2] FEC_TXD[1] FEC_TXER DTOUT3 DTOUT2 DTOUT1 DTOUT0 CANRX4 CANTX4 -- --
Tertiary Function URXD1 UTXD1 URTS1 SYNCB FEC_TXCLK FEC_TXEN UCTS1 -- -- -- PWM7 PWM5 PWM3 PWM1 PWM6 PWM4 PWM2 PWM0 FEC_RXCLK FEC_RXDV FEC_RXD[0] FEC_CRS
Drive Quaternary Strength/ Function Control1 PQS[1] PQS[0] PQS[2] PQS[6] PQS[5] PQS[4] PQS[3] -- -- -- PTA[3] PTA[2] PTA[1] PTA[0] PTC[3] PTC[2] PTC[1] PTC[0] PUA[3] PUA[2] PUA[1] PUA[0] PDSR[2] PDSR[1] PDSR[3] PDSR[7] PDSR[6] PDSR[5] PDSR[4] N/A high N/A PDSR[23] PDSR[22] PDSR[21] PDSR[20] PDSR[19] PDSR[18] PDSR[17] PDSR[16] PDSR[11] PDSR[10] PDSR[9] PDSR[8]
Wired OR Control PWOR[4] PWOR[5] PWOR[6] -- -- -- PWOR[7] N/A -- N/A -- -- -- -- -- -- -- -- -- -- PWOR[0] PWOR[1]
Pull-up/ Pull-down2 -- -- Pull-Up8 -- -- -- Pull-Up8 Pull-Up9 -- Pull-Down Pull-Up10 Pull-Up10 Pull-Up10 Pull-Up -- -- -- -- -- -- -- --
10
Pin on 121 MAPBGA H4 J4 K4 K5 J5 H5 L4 J6 L6 H7 B4 C4 D4 B3 H1 G1 D1 D2 J2 H2 K2 L2
Pin on 112 LQFP 34 35 36 40 39 38 37 44 46 50 107 108 109 110 22 21 9 8 26 25 30 31
Pin on 80 LQFP 25 26 27 -- -- -- 28 32 34 38 75 76 77 78 14 13 9 8 18 17 21 22
UCTS0 URTS0 URXD0 UTXD0
Freescale Semiconductor
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group UART 13 Primary Function UCTS1 URTS1 URXD1 UTXD1 UART 2 MCF52235 ColdFire Microcontroller, Rev. 7 UCTS2 URTS2 URXD2 UTXD2 FlexCAN SYNCA SYNCB VDD
5,11
Freescale Semiconductor 21
SecondaryF unction SYNCA SYNCB -- -- -- -- -- -- CANTX
4
Tertiary Function URXD2 UTXD2 FEC_TXD[0] FEC_COL -- -- -- -- FEC_MDIO FEC_MDC -- -- -- --
Drive Quaternary Strength/ Function Control1 PUB[3] PUB[2] PUB[1] PUB[0] PUC[3] PUC[2] PUC[1] PUC[0] PAS[3] PAS[2] -- -- -- -- PDSR[15] PDSR[14] PDSR[13] PDSR[12] PDSR[27] PDSR[26] PDSR[25] PDSR[24] PDSR[39] PDSR[39] N/A N/A N/A N/A
Wired OR Control -- -- PWOR[2] PWOR[3] -- -- -- -- -- -- N/A N/A N/A N/A
Pull-up/ Pull-down2 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Pin on 121 MAPBGA J3 H3 K3 L3 L10 K10 K11 L11 -- -- D7, E8 D5, D6, E6, G5, G6, G7, H6 E4, E5, E7,F4, F5, F6, F7, F8 --
Pin on 112 LQFP 24 23 32 33 61 60 62 63 28 27 65,102 14, 43 64,101 15, 42
Pin on 80 LQFP 16 15 23 24 -- -- -- -- 20 19 45,74 10, 31 44,73 11, 30
CANRX4 -- -- -- --
VDD VDDX VSS VSSX
VDDX VSS VSSX
1
The PDSR and PSSR registers are described in Chapter 14, "General Purpose I/O Module. All programmable signals default to 2mA drive in normal (single-chip) mode. 2 All signals have a pull-up in GPIO mode. 3 The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins. 4 The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals. 5 The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them. 6 For primary and GPIO functions only. 7 Only when JTAG mode is enabled. 8 For secondary and GPIO functions only. 9 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended. 10 For GPIO function. Primary Function has pull-up control within the GPT module. 11 This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.
MCF52235 Family Configurations
1.3
Reset Signals
Table 4. Reset Signals
Signal Name Reset In Reset Out Abbreviation RSTI RSTO Function Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals. Driven low for 512 CPU clocks after the reset source has deasserted. I/O I O
Table 4 describes signals that are used to either reset the chip or as a reset indication.
1.4
PLL and Clock Signals
Table 5. PLL and Clock Signals
Signal Name External Clock In Crystal Clock Out Abbreviation EXTAL XTAL CLKOUT Function Crystal oscillator or external clock input. Crystal oscillator output. This output signal reflects the internal system clock. I/O I O O
Table 5 describes signals that are used to support the on-chip clock generation circuitry.
1.5
Mode Selection
Table 6. Mode Selection Signals
Signal Name Reset Configuration Abbreviation RCON Function The Serial Flash Programming mode is entered by asserting the RCON pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the Flash memory which can be programmed from an external device. Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions. I/O --
Table 6 describes signals used in mode selection, Table 6 describes particular clocking modes.
Test
TEST
I
1.6
External Interrupt Signals
Table 7. External Interrupt Signals
Signal Name External Interrupts Abbreviation IRQ[15:1] External interrupt sources. Function I/O I
Table 7 describes the external interrupt signals.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 22 Freescale Semiconductor
MCF52235 Family Configurations
1.7
Queued Serial Peripheral Interface (QSPI)
Table 8. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name QSPI Synchronous Serial Output QSPI Synchronous Serial Data Input QSPI Serial Clock Abbreviation Function I/O O I O O
Table 8 describes QSPI signals.
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPI_CLK. QSPI_DIN QSPI_CLK Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK. Provides the serial clock from the QSPI. The polarity and phase of QSPI_CLK are programmable.
Synchronous Peripheral QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active Chip Selects high or low.
1.8
Fast Ethernet Controller EPHY Signals
Table 9. Fast Ethernet Controller (FEC) Signals
Signal Name Twisted Pair Input + Twisted Pair Input Twisted Pair Output + Twisted Pair Output Bias Control Resistor Abbreviation RXP RXN TXN TXP RBIAS Function Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset. Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset. Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset. Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset. Connect a 12.4 k (1.0%) external resistor, RBIAS, between the PHY_RBIAS pin and analog ground. Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF (>50 pF causes instability). No high-speed signals can be permitted in the region of RBIAS. Indicates when the EPHY is transmitting or receiving Indicates when the EPHY has a valid link Indicates the speed of the EPHY connection Indicates the duplex (full or half) of the EPHY connection Indicates if the EPHY detects a collision Indicates if the EPHY is transmitting Indicates if the EPHY is receiving I/O I I O O I
Table 9 describes the Fast Ethernet Controller (FEC) signals.
Activity LED Link LED Speed LED Duplex LED Collision LED Transmit LED Receive LED
ACT_LED LINK_LED SPD_LED DUPLED COLLED TXLED RXLED
O O O O O O O
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 23
MCF52235 Family Configurations
1.9
I2C I/O Signals
Table 10. I2C I/O Signals
Signal Name Serial Clock Abbreviation SCL Function Open-drain clock signal for the for the I2C interface. Either it is driven by the I2C module when the bus is in master mode or it becomes the clock input when the I2C is in slave mode. Open-drain signal that serves as the data input/output for the I2C interface. I/O I/O
Table 10 describes the I2C serial interface module signals.
Serial Data
SDA
I/O
1.10
UART Module Signals
Table 11. UART Module Signals
Signal Name Abbreviation UTXDn Function Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source. Receiver serial data inputs for the UART modules. Data is received on this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it. Indicate to the UART modules that they can begin data transmission. Automatic request-to-send outputs from the UART modules. This signal can also be configured to be asserted and negated as a function of the RxFIFO level. I/O O
Table 11 describes the UART module signals.
Transmit Serial Data Output
Receive Serial Data Input Clear-to-Send Request-to-Send
URXDn
I
UCTSn URTSn
I O
1.11
DMA Timer Signals
Table 12. DMA Timer Signals
Signal Name DMA Timer Input Abbreviation DTINn DTOUTn Function Event input to the DMA timer modules. Programmable output from the DMA timer modules. I/O I O
Table 12 describes the signals of the four DMA timer modules.
DMA Timer Output
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 24 Freescale Semiconductor
MCF52235 Family Configurations
1.12
ADC Signals
Table 13. ADC Signals
Signal Name Analog Inputs Analog Reference Abbreviation AN[7:0] VRH VRL Analog Supply VDDA VSSA Isolate the ADC circuitry from power supply noise Function Inputs to the A-to-D converter. Reference voltage high and low inputs. I/O I I I -- --
Table 13 describes the signals of the Analog-to-Digital Converter.
1.13
General Purpose Timer Signals
Table 14. GPT Signals
Signal Name Abbreviation GPT[3:0] Function Inputs to or outputs from the general purppose timer module I/O I/O
Table 14 describes the General Purpose Timer Signals.
General Purpose Timer Input/Output
1.14
Pulse Width Modulator Signals
Table 15. PWM Signals
Signal Name Abbreviation PWM[7:0] Function Pulse width modulated output for PWM channels I/O O
Table 15 describes the PWM signals.
PWM Output Channels
1.15
Debug Support Signals
Table 16. Debug Support Signals
Signal Name JTAG Enable Test Reset Test Clock Test Mode Select Test Data Input Abbreviation JTAG_EN TRST TCLK TMS TDI Function Select between debug module and JTAG signals at reset This active-low signal is used to initialize the JTAG logic asynchronously. Used to synchronize the JTAG logic. Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK. Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK. I/O I I I I I
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 25
MCF52235 Family Configurations
Table 16. Debug Support Signals (continued)
Signal Name Test Data Output Abbreviation TDO Function Serial output for test instructions and data. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK. Development Serial Clock. Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state. Breakpoint. Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor. Development Serial Input. Internally synchronized input that provides data input for the serial communication port to the debug module after the DSCLK has been seen as high (logic 1). Development Serial Output. Provides serial output communication for debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high. Display captured processor data and breakpoint status. The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0]. Processor Status Clock. Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values. If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST, and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be re-enabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs. PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during system reset exception processing. Indicate core status. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The CLKOUT signal can be used by the development system to know when to sample PST[3:0]. Logical AND of PST[3:0] I/O O
Development Serial Clock
DSCLK
I
Breakpoint
BKPT
I
Development Serial Input Development Serial Output Debug Data
DSI
I
DSO
O
DDATA[3:0]
O
Processor Status Clock
PSTCLK
O
Processor Status Outputs
PST[3:0]
O
All Processor Status Outputs
ALLPST
O
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 26 Freescale Semiconductor
MCF52235 Family Configurations
1.16
EzPort Signal Descriptions
Table 17. EzPort Signal Descriptions
Signal Name EzPort Clock EzPort Chip Select EzPort Serial Data In EzPort Serial Data Out Abbreviation EZPCK EZPCS EZPD EZPQ Function Shift clock for EzPort transfers Chip select for signalling the start and end of serial transfers EZPD is sampled on the rising edge of EZPCK EZPQ transitions on the falling edge of EZPCK I/O I I I O
Table 17 contains a list of EzPort external signals
1.17
Power and Ground Pins
Table 18. Power and Ground Pins
Signal Name Abbreviation VDDPLL, VSSPLL VDD VSS Function Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply. These pins supply positive power to the core logic. This pin is the negative supply (ground) to the chip. I/O I
The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.
PLL Analog Supply
Positive Supply Ground
I --
Some of the VDD and VSS pins on the device are only to be used for noise bypass. Figure 5 shows a typical connection diagram. Pay particular attention to those pins which show only capacitor connections. Do not connect power supply voltage directly to these pins.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 27
Electrical Characteristics
VDDPLL VSSPLL VDDA VRH VRL VSSA VDDR VSSX1 MCF52235 VDDX1 VDDX2 Pin numbering is shown for the 80-pin LQFP VSSX2 VDD2 VSS2 VDD1 PHY_RBIAS PHY_VDDRX PHY_VDDTX PHY_VDDA VSS1
33 35 69 70 71 72 58 11 10 31 30 45 44 74 73 0.22F 0.22F 0.1F 0.1F 0.1F 3.3V 0.1F 0.1F 10H * 10F 10V Tantalum 0.22F 1000pF
46
55
49
12.4K 1%
0.22F 0.22F 0.22F *optional
Figure 5. Suggested Connection Scheme for Power and Ground
2
Electrical Characteristics
NOTE
The parameters specified in this appendix supersede any values found in the module specifications.
This section contains electrical specification tables and reference timing diagrams for the MCF52235, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 28 Freescale Semiconductor
48
Electrical Characteristics
2.1
Maximum Ratings
Table 19. Absolute Maximum Ratings1, 2
Rating Supply voltage Clock synthesizer supply voltage Digital input voltage EXTAL pin voltage XTAL pin voltage Instantaneous maximum current Single pin limit (applies to all pins) 4, 5 Operating temperature range (packaged) Storage temperature range
1 3
Symbol VDD VDDPLL VIN VEXTAL VXTAL IDD TA (TL - TH) Tstg
Value -0.3 to +4.0 -0.3 to +4.0 -0.3 to + 4.0 0 to 3.3 0 to 3.3 25 -40 to 85 -65 to 150
Unit V V V V V mA C C
2
3
4 5
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). Input must be current limited to the IDD value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and VDD. The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power (ex; no clock). The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
Table 20 lists thermal resistance values.
NOTE
The use of this device in one- or two-layer board designs is not recommended due to the limited thermal conductance provided by those boards.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 29
Electrical Characteristics
Table 20. Thermal Characteristics
Characteristic Junction to ambient, natural convection Symbol JA Package1 80-pin LQFP, four-layer board 112-pin LQFP, four-layer board 121 MAPBGA, four-layer board 80-pin LQFP, one-layer board1 Value 36.0
2,3
Unit C/W
35.0 32 49.01 561 44.01 30.0 29.0 28 39.01 35.01 461 22.04 23.0 18 6.05 6.0 10 2.06 2.0
6
121 MAPBGA, one-layer board1 112-pin LQFP, one-layer board1 Junction to ambient (@200 ft/min) JMA 80-pin LQFP, four-layer board 112-pin LQFP, four-layer board 121 MAPBGA, four-layer board 80-pin LQFP, one-layer board1 112-pin LQFP, one-layer board1 121 MAPBGA, one-layer board1 Junction to board JB 80-pin LQFP 112-pin LQFP 121 MAPBGA, four-layer board Junction to case JC 80-pin LQFP 112-pin LQFP 121 MAPBGA Junction to top of package, natural convection jt 80-pin LQFP 112-pin LQFP 121 MAPBGA Maximum operating junction temperature
1 2
C/W
C/W
C/W
C/W
2.06 130
oC
Tj
All
3 4 5 6
The use of this device in one- or two-layer board designs is not recommended due to the limited thermal conductance provided by those boards. JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JMA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 30 Freescale Semiconductor
Electrical Characteristics
The average chip-junction temperature (TJ) in C can be obtained from T J = T A + ( P D x JMA ) where * * * * * TA = ambient temperature, C JMA = package thermal resistance, junction-to-ambient, C/W PD = PINT + PI/O PINT = chip internal power, IDD x VDD, watts PI/O = power dissipation on input and output pins -- user determined Eqn. 1
For most applications, PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K / ( T J + 273C ) Solving equations 1 and 2 for K gives: K = P D x ( T A + 273C ) + JMA x P D
2
Eqn. 2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
2.2
ESD Protection
Table 21. ESD Protection Characteristics1
Characteristic ESD target for Human Body Model ESD target for Charged Device Model HBM circuit description Number of pulses per pin (HBM) positive pulses negative pulses Number of pulses per pin (CDM) positive pulses negative pulses Interval of pulses (HBM) Interval of pulses (CDM)
1
Symbol HBM CDM Rseries C -- -- -- -- -- --
Value 1500 (ADC and EPHY pins) 2000 (All other pins) 250 1500 100 1 1
Units V V ohms pF --
-- 3 3 1.0 0.2 sec sec
A device is defined as a failure if the device no longer meets the device specification requirements after exposure to ESD pulses. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 31
Electrical Characteristics
2.3
DC Electrical Specifications
Table 22. DC Electrical Specifications 1
Characteristic Symbol VDD VIH VIL VHYS VLVD VLVDHYS Iin IOZ VOH VOL IAPU Cin -- -- CL IIC -1.0 -10 1.0 10 7 7 pF 25 50 mA Min 3.0 0.7 x VDD VSS - 0.3 0.06 x VDD 2.15 60 -1.0 -1.0 VDD - 0.5 __ -10 Max 3.6 4.0 0.35 x VDD -- 2.3 120 1.0 1.0 __ 0.5 -130 Unit V V V mV V mV A A V V A pF
Supply voltage Input high voltage Input low voltage Input hysteresis Low-voltage detect trip voltage (VDD falling) Low-voltage detect hysteresis (VDD rising) Input leakage current Vin = VDD or VSS, input-only pins High impedance (off-state) leakage current Vin = VDD or VSS, all input/output and output pins Output high voltage (all input/output and all output pins) IOH = -2.0 mA Output low voltage (all input/output and all output pins) IOL = 2.0 mA Weak internal pull-up device current, tested at VIL max.2 Input capacitance 3 All input-only pins All input/output (three-state) pins Load capacitance4 Low drive strength High drive strength DC injection current 3, 5, 6, 7 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single pin limit Total MCU limit, Includes sum of all stressed pins
1 2 3 4 5 6 7
Refer to Table 25 for additional PLL specifications. Refer to Table 3 for pins with internal pull-up devices. This parameter is characterized before qualification rather than 100% tested. pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. All functional non-supply pins are internally clamped to VSS and their respective VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. The power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that the external VDD load shunts current greater than maximum injection current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, the system clock is not present during the power-up sequence until the PLL has attained lock.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 32 Freescale Semiconductor
Electrical Characteristics
Table 23. Active Current Consumption Specifications
Typical Characteristic Symbol Running from Running from Running from Running from SRAM, Flash, Flash, EPHY Flash, EPHY EPHY Off EPHY Off 10BaseT 100BaseT 75 130 20 15 82 138 20 15 150 220 20 15 260 310 20 15 Peak Unit
Active current, core and I/O IDDR+IDDX +IDDA PLL @25 MHz PLL @60 MHz Analog supply current Normal operation Low-power STOP IDDA
290 340 30 50
mA
mA A
Table 24. Current Consumption Specifications in Low-Power Modes1
Mode2 STOP mode 3 (STPMD[1:0]=11) STOP mode 2 (STPMD[1:0]=10) STOP mode 1 (STPMD[1:0]=01) STOP mode 0 (STPMD[1:0]=00) WAIT DOZE RUN
1 2
PLL @25 MHz (typical)3 7 10 10 16 16 25
PLL @60 MHz (typical)3
PLL @60 MHz (peak)4 1.0 --
Unit mA
0.2 12 12 27 27 45
-- -- -- -- --
All values are measured with a 3.30 V power supply. Refer to the "Power Management" chapter in the MCF52235 ColdFire(R) Integrated Microcontroller Reference Manual for more information on low-power modes. 3 These values were obtained with CLKOUT and all peripheral clocks except for the CFM clock disabled prior to entering low-power mode. The tests were performed at room temperature. All code was executed from flash memory; running code from SRAM further reduces power consumption. 4 These values were obtained with CLKOUT and all peripheral clocks enabled. All code was executed from flash memory.
2.4
Phase Lock Loop Electrical Specifications
Table 25. PLL Electrical Specifications
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Symbol fref_crystal fref_ext fsys 0 fref / 32 fLOR fSCM 100 1
4, 5
Min 2 2
Max 10.0 10.0
Unit MHz
PLL reference frequency range1 Crystal reference External reference System frequency 2 External clock mode On-Chip PLL Frequency Loss of reference frequency 3, 5 Self clocked mode frequency
MHz 60 60 1000 5 kHz MHz
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 33
Electrical Characteristics
Table 25. PLL Electrical Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Crystal start-up time
5, 6
Symbol tcst VIHEXT
Min -- VDD- 1.0 2.0
Max 10 VDD VDD
Unit ms V
EXTAL input high voltage Crystal reference External reference EXTAL input low voltage Crystal reference External reference XTAL output high voltage IOH = 1.0 mA XTAL output low voltage IOL = 1.0 mA XTAL load capacitance7 PLL lock time5,9
5, 7,8
VILEXT VSS VSS VOL VDD -1.0 VOL -- -- tlpll tlplk -- -- tdc fUL fLCK Cjitter -- -- 10 .01 40 -1.5 -0.75 10.5 500 60 1.5 0.75 -- 0.5 -- 500 -- 1.0 0.8
V
V V pF s ms s % fsys % fsys % fsys % fsys
Power-up to lock time With crystal reference Without crystal reference Duty cycle of reference 5 Frequency un-LOCK range Frequency LOCK range CLKOUT period Jitter 5, 6, 8, 9,10, measured at fSYS Max Peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over 2 ms interval)
1
Input to the PLL is limited to 10 MHz max; however, the PLL divider can accept up to 40 MHz. The input must be divided down to a frequency no greater than 10 MHz. This is controlled by register CCHR. 2 All internal registers retain data at 0 Hz. 3 Loss of reference frequency is the reference frequency detected internally that transitions the PLL into self-clocked mode. 4 Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f LOR with default MFD/RFD settings. 5 This parameter is characterized before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. 7 Load capacitance determined from crystal manufacturer specifications and include circuit board parasitics. 8 Assuming a reference is available at power up, lock time is measured from the time V DD and VDDPLL are valid to RSTO negating. If the crystal oscillator is the reference for the PLL, the crystal start up time must be added to the PLL lock time to determine the total start-up time. 9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval 10 Based on slow system clock of 40 MHz measured at f sys max.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 34 Freescale Semiconductor
Electrical Characteristics
2.5
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, timers, UARTs, FEC, interrupts and USB interfaces. When in GPIO mode, the timing specification for these pins is given in Table 26 and Figure 6. The GPIO timing is met under the following load test conditions: * * 50 pF / 50 for high drive 25 pF / 25 for low drive Table 26. GPIO Timing
Num G1 G2 G3 G4 Characteristic CLKOUT high to GPIO output valid CLKOUT high to GPIO output invalid GPIO input valid to CLKOUT high CLKOUT high to GPIO input invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
CLKOUT
G1 G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 6. GPIO Timing
2.6
Reset Timing
Table 27. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
Num R1 R2 R3 R4
1 2
Characteristic RSTI input valid to CLKOUT high CLKOUT high to RSTI input invalid RSTI input valid time
2
Symbol tRVCH tCHRI tRIVT tCHROV
Min 9 1.5 5 --
Max -- -- -- 10
Unit ns ns tCYC ns
CLKOUT high to RSTO valid
All AC timing is shown with respect to 50% VDD levels unless otherwise noted. During low power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system. Therefore, RSTI must be held a minimum of 100ns.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 35
Electrical Characteristics
CLKOUT
1R1 R2 R3 R4 R4
RSTI
RSTO
Figure 7. RSTI and Configuration Override Timing
2.7
I2C Input/Output Timing Specifications
Table 28. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 x tCYC 8 x tCYC -- 0 -- 4 x tCYC 0 2 x tCYC 2 x tCYC Max -- -- 1 -- 1 -- -- -- -- Units ns ns ms ns ms ns ns ns ns
Table 28 lists specifications for the I2C input timing parameters shown in Figure 8.
Table 29 lists specifications for the I2C output timing parameters shown in Figure 8.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 36 Freescale Semiconductor
Electrical Characteristics
Table 29. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I1 1 I2 I3
1 2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 x tCYC 10 x tCYC -- 7 x tCYC -- 10 x tCYC 2 x tCYC 20 x tCYC 10 x tCYC
Max -- -- -- -- 3 -- -- -- --
Units ns ns s ns ns ns ns ns ns
I4 1 I5 3 I6 1 I7 I8
1 1
I9 1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 29 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 8 shows timing for the values in Table 28 and Table 29.
I2 SCL I6 I5 I3
I1
I4
I7
I8
I9
SDA
Figure 8. I2C Input/Output Timings
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 37
Electrical Characteristics
2.8
2.8.1
EPHY Parameters
EPHY Timing
Table 30. EPHY Timing Parameters
Num E1 Characteristic EPHY startup time Symbol tStart-Up Value 360 Unit s
Table 30 and Figure 9 show the relevant EPHY timing parameters.
EPHYEN
MDIO
E1
Figure 9. EPHY Timing
2.8.2
10BASE-T SQE (Heartbeat) Timing
Table 31. 10BASE-T SQE (Heartbeat) Timing Parameters
Characteristic COL (SQE) delay after TXEN off COL (SQE) pulse duration
1
Table 31 and Figure 10 show the relevant 10BASE-T SQE (heartbeat) timing parameters.
Symbol t1 t2
Min -- --
Typ1 1.0 1.0
Max -- --
Units s s
Typical values are at 25C.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 38 Freescale Semiconductor
Electrical Characteristics
TXC
TXEN
t1
t2
COL
Figure 10. 10BASE-T SQE (Heartbeat) Timing
2.8.3
10BASE-T Jab and Unjab Timing
Table 32. 10BASE-T Jab and Unjab Timing Parameters
Parameter Maximum transmit time Unjab time
1
Table 32 and Figure 11 show the relevant 10BASE-T jab and unjab timing parameters.
Symbol t1 t2
Min -- --
Typ1 98 525
Max -- --
Units ms ms
Typical values are at 25C.
TXEN
t1
TXD
COL
t2
Figure 11. 10BASE-T Jab and Unjab Timing
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 39
Electrical Characteristics
2.8.4
Transceiver Characteristics
Table 33. 10BASE-T Transceiver Characteristics
Parameter Symbol VOP -- Zin Vsquelch Min 2.2 0 -- 300 Typ 2.5 2 10 400 Max 2.8 11 -- 585 Units V ns k mV Test Conditions With specified transformer and line replaced by 100 (1%) load Using line model specified in the IEEE 802.3 0.0 < Vin < 3.3 V 3.3 MHz sine wave input
Peak differential output voltage Transmit timing jitter Receive dc input impedance Receive differential squelch level
Table 34. 100BASE-TX Transceiver Characteristics
Parameter Transmit Peak Differential Output Voltage Transmit Signal Amplitude Symmetry Transmit Rise/Fall Time Transmit Rise/Fall Time Symmetry Transmit Overshoot/UnderShoot Transmit Jitter Receive Common Mode Voltage Receiver Maximum Input Voltage Symbol VOP Vsym trf trfs Vosh -- Vcm Vmax Min 0.95 98 3 -0.5 -- 0 -- -- Typ 1.00 100 4 0 2.5 .6 1.6 -- Max 1.05 102 5 +0.5 5 1.4 -- 4.7 Units V % ns ns % ns V V VDDRX = 2.5 V VDDRX = 2.5 V. Internal circuits protected by divider in shutdown Test Conditions With specified transformer and line replaced by 100 (1%) load With specified transformer and line replaced by 100 (1%) load With specified transformer and line replaced by 100 (1%) load See IEEE 802.3 for details
2.9
Analog-to-Digital Converter (ADC) Parameters
Table 35 lists specifications for the analog-to-digital converter. Table 35. ADC Parameters1
Name VREFL VREFH VDDA VADIN RES INL INL DNL Characteristic Low reference voltage High reference voltage Analog supply voltage Input voltages Resolution Integral non-linearity (full input signal range)
2
Min VSS VREFL 3.0 VREFL 12 -- -- --
Typical -- -- 3.3 -- -- 2.5 2.5 -1 < DNL < +1
Max VREFH VDDA 3.6 VREFH 12 3 3 <+1
Unit V V V V bits LSB3 LSB LSB
Integral non-linearity (10% to 90% input signal range)4 Differential non-linearity Monotonicity
Guaranteed
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 40 Freescale Semiconductor
Electrical Characteristics
Table 35. ADC Parameters1 (continued)
Name fADIC RAD tADPU tREC tADC tADS CADI XIN IADI IVREFH VOFFSET EGAIN VOFFSET SNR THD SFDR SINAD ENOB
1 2 3 4 5 6 7
Characteristic ADC internal clock Conversion range ADC power-up time
5
Min 0.1 VREFL -- -- -- -- -- --
Typical -- -- 6 0 6 1 See Figure 12 See Figure 12 -- 0 11 1 3 62 to 66 -75 75 65 10.6
Max 5.0 VREFH 13 1 -- -- -- -- 3 -- 15 1.01 -- -- -- -- -- --
Unit MHz V tAIC cycles6 tAIC cycles tAIC cycles tAIC cycles pF W mA mA mV -- mV dB dB dB dB Bits
Recovery from auto standby Conversion time Sample time Input capacitance Input impedance Input injection current , per pin VREFH current Offset voltage internal reference Gain error (transfer path) Offset voltage external reference Signal-to-noise ratio Total harmonic distortion Spurious free dynamic range Signal-to-noise plus distortion Effective number OF bits
7
-- -- -- .99 -- -- -- -- -- 9.1
All measurements were made at VDD = 3.3V, VREFH = 3.3V, and VREFL = ground INL measured from VIN = VREFL to VIN = VREFH LSB = Least Significant Bit INL measured from VIN = 0.1VREFH to VIN = 0.9VREFH Includes power-up of ADC and VREF ADC clock cycles The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
2.9.1
Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFH-VREFL)/2, while the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended analog input is switched to a differential voltage centered about (VREFH-VREFL)/2. The switches switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides isolation during the charge-sharing phase. One aspect of this circuit is that there is an ongoing input current, which is a function of the analog input voltage, VREF, and the ADC clock frequency.
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 41
Electrical Characteristics
125W ESD Resistor
8pF noise damping capacitor
Analog Input
3 S1
4 C1 S3 S/H C2 C1 = C2 = 1pF
1
2
(VREFH- VREFL) / 2
S2
1 2
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF 3 Equivalent resistance for the channel select mux; 100 ohms 4 Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pF 1 5 Equivalent input impedance, when the input is selected = ----------------------------------------------------------------------------------------- 12 ADC CLOCK RATE x ( 1.4 x 10 )
Figure 12. Equivalent Circuit for A/D Loading
2.10
DMA Timers Timing Specifications
Table 36. Timer Module AC Timing Specifications
Name T1 T2 Characteristic1 DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width Min 3 x tCYC 1 x tCYC Max -- -- Unit ns ns
Table 36 lists timer module AC timings.
1
All timing references to CLKOUT are given to its rising edge.
2.11
Name EP1 EP1a EP2 EP3 EP4 EP5 EP6
EzPort Electrical Specifications
Table 37. EzPort Electrical Specifications
Characteristic EPCK frequency of operation (all commands except READ) EPCK frequency of operation (READ command) EPCS_b negation to next EPCS_b assertion EPCS_B input valid to EPCK high (setup) EPCK high to EPCS_B input invalid (hold) EPD input valid to EPCK high (setup) EPCK high to EPD input invalid (hold) Min -- -- 2 x Tcyc -- 5 -- 5 Max fsys / 2 fsys / 8 -- 5 -- 2 -- Unit MHz MHz ns ns ns ns ns
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 42 Freescale Semiconductor
Electrical Characteristics
Table 37. EzPort Electrical Specifications (continued)
Name EP7 EP8 EP9 Characteristic EPCK low to EPQ output valid (out setup) EPCK low to EPQ output invalid (out hold) EPCS_B negation to EPQ tri-state Min -- 0 -- Max 12 -- 12 Unit ns ns ns
2.12
QSPI Electrical Specifications
Table 38. QSPI Modules AC Timing Specifications
Table 38 lists QSPI timings.
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[3:0] to QSPI_CLK
Characteristic
Min 1 -- 2 9 9
Max 510 10 -- -- --
Unit tCYC ns ns ns ns
QSPI_CLK high to QSPI_DOUT valid QSPI_CLK high to QSPI_DOUT invalid (output hold) QSPI_DIN to QSPI_CLK (input setup) QSPI_DIN to QSPI_CLK (input hold)
The values in Table 38 correspond to Figure 13.
QS1 QSPI_CS[3:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 13. QSPI Timing
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 43
Electrical Characteristics
2.13
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14
1
JTAG and Boundary Scan Timing
Table 39. JTAG and Boundary Scan Timing
Characteristics1 TCLK frequency of operation TCLK cycle period TCLK clock pulse width TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high Z TRST assert time TRST setup time (negation) to TCLK high Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 x tCYC 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/2 ns ns ns ns ns ns ns ns ns ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2 J3 J3
TCLK (input) J4
VIH VIL J4
Figure 14. Test Clock Input Timing
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 44 Freescale Semiconductor
Electrical Characteristics
TCLK
VIL J5
VIH J6
Data Inputs J7 Data Outputs J8 Data Outputs J7 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
Figure 15. Boundary Scan (JTAG) Timing
TCLK VIL J9 TDI TMS J11 TDO J12 TDO J11 TDO Output Data Valid Output Data Valid VIH J10
Input Data Valid
Figure 16. Test Access Port Timing
TCLK 14 TRST 13
Figure 17. TRST Timing
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 45
Electrical Characteristics
2.14
Debug AC Timing Specifications
Table 40. Debug AC Timing Specification
60 MHz Num D1 D2 D3 D4
1
Table 40 lists specifications for the debug AC timing parameters shown in Figure 19.
Characteristic Min PST, DDATA to CLKOUT setup CLKOUT to PST, DDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT input data setup time to CLKOUT Rise BKPT input data hold time to CLKOUT Rise CLKOUT high to BKPT high Z 4 1.5 1 x tCYC 4 x tCYC 5 x tCYC 4 1.5 0.0 Max -- -- -- -- -- -- -- 10.0
Units ns ns ns ns ns ns ns ns
D5 D6 D7 D8
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 18 shows real-time trace timing for the values in Table 40.
CLKOUT
D1
D2
PST[3:0] DDATA[3:0]
Figure 18. Real-Time Trace AC Timing Figure 19 shows BDM serial port AC timing for the values in Table 40.
CLKOUT D5 DSCLK D3 DSI Current D4 DSO Past Current Next
Figure 19. BDM Serial Port AC Timing
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 46 Freescale Semiconductor
Mechanical Outline Drawings
3
3.1
Mechanical Outline Drawings
80-pin LQFP Package
4X 4X 20 TIPS
This section describes the physical properties of the MCF52235 and its derivatives.
-X-
X= L, M, N
0.20 (0.008) H L-M N
80 1 61 60
0.20 (0.008) T L-M N C L AB AB -M- VIEW Y B V J
PLATING
P
G
-L-
3X
VIEW Y B1
F
V1
BASE METAL
20 21 40
41
-N- A1 S1 A S
0.13 (0.005)
SECTION AB-AB
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z 0 01 02 MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC --- 1.60 0.04 0.24 1.30 1.50 0.22 0.38 0.40 0.75 0.17 0.33 0.65 BSC 0.09 0.27 0.50 REF 0.325 BSC 0.10 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 10 0 --- 9 14 INCHES MIN MAX 0.551 BSC 0.276 BSC 0.551 BSC 0.276 BSC --- 0.063 0.002 0.009 0.051 0.059 0.009 0.015 0.016 0.030 0.007 0.013 0.026 BSC 0.004 0.011 0.020 REF 0.013 REF 0.004 0.008 0.630 BSC 0.315 BSC 0.004 0.006 0.630 BSC 0.315 BSC 0.008 REF 0.039 REF 0 10 0 --- 9 14
C -H- -T-
SEATING PLANE
8X
2
0.10 (0.004) T
VIEW AA (W) C2 0.05 (0.002)
S
1
2X R R1
0.25 (0.010)
GAGE PLANE
(K) C1 E (Z)
VIEW AA
CASE 917A-02 ISSUE C DATE 09/21/95
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 47
ICCC CCC III IIII
D U
M
T L-M
S
N
S
Mechanical Outline Drawings
3.2
112-pin LQFP Package
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 48 Freescale Semiconductor
Mechanical Outline Drawings
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 49
Mechanical Outline Drawings
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 50 Freescale Semiconductor
Mechanical Outline Drawings
3.3
121 MAPBGA Package
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 51
Mechanical Outline Drawings
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 52 Freescale Semiconductor
Revision History
4
Revision History
Table 41. Revision History
Revision 2 (Jul 2006) * Updated available packages. * Inserted mechanical drawings. * Corrected signal pinouts and table. * Changed signal names TIN to DTIN and TOUT to DTOUT to match the MCF52235 ColdFire(R) Integrated Microcontroller Reference Manual. * Added overbars to extend over entire UCTSn and URTSn signal name. * Added revision history. * Formatting, layout, spelling, and grammar corrections. * Updated block diagram and feature information to match Revision 3 of the MCF52235 ColdFire(R) Integrated Microcontroller Reference Manual. * Deleted the "PSTCLK cycle time" row from the "Debug AC Timing Specifications" table. * Added "EPHY Timing" section. * Deleted the "RAM standby supply voltage" entry from Table 19. * Changed the minimum value for SNR, THD, SFDR, and SINAD in the "ADC parameters" table (was TBD, is "--"). * In the "Pin Functions by Primary and Alternate Purpose" table, changed the pin number for IRQ11 on the 80 LQFP package (was "--", is 41). * Updated the "Thermal characteristics" table to include proper thermal resistance values. * Added two tables, "Active Current Consumption Specifications" and "Current Consumption Specifications in Low-Power Modes", containing the latest current consumption information. * Changed the value of Tj in the "Thermal Characteristics" table (was 105 C, is 130 C for all packages). * Added the following note to and above the "Thermal Characteristics" table: "The use of this device in one- or two-layer board designs is not recommended due to the limited thermal conductance provided by those boards." * Added the value for jt for the 121MAPBGA package (2.0 C/W). * Formatting, layout, spelling, and grammar corrections. * Added load test condition information to the "General Purpose I/O Timing" section. * Added specifications for VLVD and VLVDHYS to the "DC electrical specifications" table. Formatting, layout, spelling, and grammar corrections. Added information about the MCF52232 and MCF52236 devices. Revised the part number table to include full Freescale orderable part numbers. Synchronized the "Pin Functions by Primary and Alternate Purpose" table in the device reference manual and data sheet. * Added specifications for VREFL, VREFH, and VDDA to the "ADC Parameters" table. * Added several EPHY specifications. * * * * * * * * * Formatting, layout, spelling, and grammar corrections. Changed the data sheet classification (was "Product Preview", is "Advance Information"). Added the "EzPort Electrical Specifications" section. Updated the "ESD Protection" section. Changed document type from Advance Information to Technical Data. Added supported device list in subtitle. Removed preliminary text from electrical specifications section as device is fully characterized. Corrected IVREFH, VREFH current unit from "m" to "mA" in ADC specification table. Changed VOFFSET from TBD to -- in ADC specification table. * * * * Description
3 (Feb 2007)
4 (May 2007)
5 (Sep 2007)
6 (Oct 2007)
7 (Aug 2008)
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 53
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Document Number: MCF52235DS
Rev. 7 8/2008

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